Memory arrays can perform the read-out of cells by utilizing an amplifier (e.g., a sense amplifier) to detect the state of the cells. This can be accomplished by enabling a row of memory cells by activating a word-line, which places the state of the cells on bit-lines. The amplifier distinguishes the state of the cell by comparing it to a reference. A high output is flagged if the state of memory cell is higher than the reference and a low output is flagged otherwise.
However, generating a reference to compare against the amplifier output is not a trivial problem. Often, the optimal reference is centered symmetrically between the low and high values placed by the memory cell on the bit-lines. Various techniques can be used to generate this reference. For example, differential memory cells implicitly generate the reference. For instance, SRAM cells typically use a differential bit-line pair. One of the bit-lines is discharged for a cell storing a high while the other is discharged when the cell stores a low. The sense-amplifier makes its decision by comparing the pair of bit-lines.
However, the use of differential bit-lines may not be available as an option for high-density memory arrays. This is because the cell may not have the space to accommodate a pair of bit-lines. For such cells the reference generation has to be carried out explicitly.
Explicit generation of the reference is commonly carried out in DRAM cells that typically employ a dummy cell. The dummy cell is discharged on an unselected bit-line (e.g., a bit-line not connected to an active memory cell). Since DRAMs are typically implemented by discharging the charge in the memory cell on the bit-line, a mid-level reference is generated by making a dummy cell with half the capacitance of the actual memory cell and charging it to the voltage corresponding to the logic high of the cell. This technique works under the assumption that the stored voltage in the cell for logic state of zero is close to zero. Alternatively a full sized memory cell charged to the mid-level voltage can be used.
A mid-level reference can be generated when the memory cell generates a current output as a signature of the state of the cell. This current discharges the selected bit-line with the rate of discharge being different for a high “1” or low “0” voltage being stored in the cell (see, e.g., FIGS. 1A and 1B). Assume for purposes of illustration that a cell storing a logical high discharges bit-line 112 at a higher rate than the cell storing a logic low discharges bit-line 102 (see, e.g., FIG. 1B). Also assume that Ihigh and Ilow are the current generated from the cell for a high value and low value respectively. With the capacitance of each bit-line being Cbl, the voltage for the high and low states after time t is given by Vhigh and Vlow.                     Vhigh        =                              Ihigh            Cbl                    ⁢          t                                    (                  Equation          ⁢                                          ⁢          1                )                                Vlow        =                              Ilow            Cbl                    ⁢          t                                    (                  Equation          ⁢                                          ⁢          2                )            
A mid-level reference corresponds to a voltage of (Vhigh+Vlow)/2 at time t. The generation of the mid-level reference can be accomplished by discharging a bit-line with a current corresponding to the average of the high and low state discharge current (i.e., (lhigh+llow)/2). One method may accomplish this by monitoring the discharge currents of two dummy cells, one holding a zero and the other a one and averaging them using an analog current mirror based implementation.